1. Field of the Invention
The present invention relates to semiconductor memory devices. In particular, the present invention relates to a semiconductor memory device including a plurality of memory cells each having two storage areas.
2. Description of the Background Art
NROM (Nitride Read-Only Memory) is now attracting attention as one of flash EEPROMs (Electrically Erasable Programmable Read-Only Memories) that are nonvolatile semiconductor memory devices. The NROM is disclosed in U.S. Pat. No. 6,011,725.
FIG. 22 is a circuit diagram showing a configuration of a memory cell array of a conventional semiconductor memory device.
Referring to FIG. 22, the memory cell array includes a plurality of nonvolatile memory cells MCs, a plurality of bit lines BLs and a plurality of word lines WLs.
Word lines WLs are arranged in respective rows and bit lines BLs are arranged in respective columns.
Nonvolatile memory cells MCs are arranged correspondingly to the crossings of word lines WLs and bit lines BLs. Nonvolatile memory cells MCs arranged in the same row are connected in series, having respective gates connected to the same word line WL. Bit lines BLs are each placed to pass the point where two nonvolatile memory cells MCs adjacent to each other are connected.
Nonvolatile memory cells MCs each have two storage areas L1 and L2.
FIG. 23 shows a cross section of one of the nonvolatile memory cells shown in FIG. 22.
Referring to FIG. 23, the nonvolatile memory cell includes a semiconductor substrate 1, two diffusion bit lines (hereinafter referred to as diffusion layers) 7A and 7B, oxide films 8 and 10, a nitride film 9, and a control gate 21.
Two diffusion layers 7A and 7B are formed with a predetermined distance therebetween on the main surface of semiconductor substrate 1. Oxide film 8 is formed on semiconductor substrate 1 and between the two diffusion layers. Nitride film 9 is formed on oxide film 8, oxide film 10 is formed on nitride film 9, and control gate 21 is formed on oxide film 10.
The nonvolatile memory cell can accumulate electrons in each of storage areas L1 and L2 in nitride film 9. In other words, the NROM allows electrons to be accumulated in two physically different places within one cell to store 2-bit data per cell.
The electrons accumulated in storage areas L1 and L2 in nitride film 9 cannot move freely in nitride film 9 and thus stay in storage areas L1 and L2, since nitride film 9 is an insulating film.
The semiconductor memory device as discussed above is easy to manufacture and the manufacturing cost is low. The memory cell array having the nonvolatile memory cell as shown in FIG. 23 includes the diffusion bit lines and word lines orthogonal to each other as shown in FIG. 22. Here, as memory cells adjacent to each other share the same diffusion bit line, the area of the memory cell array is reduced relative to that of conventional flash EEPROMs.
Description is now given below of data writing/reading operations into/from each of the storage areas L1 and L2 of the nonvolatile memory cell MC.
FIGS. 24-27 illustrate writing/reading operations of data for the two storage areas in the nonvolatile memory cell MC.
Referring to FIG. 24, nonvolatile memory cell MC has its gate connected to word line WL, and the memory cell MC is connected to bit lines BL0 and BL1. Nonvolatile memory cell MC has its sides corresponding respectively to bit lines BL0 and BL1, and storage area L1 is placed on the side corresponding to bit line BL0 as shown in FIGS. 24 and 25 while storage area L2 is placed on the side corresponding to bit line BL1 as shown in FIGS. 26 and 27.
A writing operation for storage area L1 is described first. Referring to FIG. 24, data is written into storage area L1 by maintaining the potential on bit line BL0 at a write potential VCCW and maintaining the potential on bit line BL1 at a ground potential GND to cause a write current Ifw to flow from bit line BL0 to bit line BL1 through nonvolatile memory cell MC. Data is thus written into storage area L1.
Next, a reading operation for storage area L1 is described. Referring to FIG. 25, data in storage area L1 is read by maintaining the potential on bit line BL0 at ground potential GND and maintaining the potential on bit line BL1 at a read potential VCCR to cause a read current Ifr to flow from bit line BL1 to bit line BL0. The data is accordingly read from storage area L1.
It is seen from the above that, in storage area L1, the direction in which the current flows in the writing operation is opposite to that of the current flowing in the reading operation.
A writing operation for storage area L2 is now described. Referring to FIG. 26, data is written into storage area L2 by maintaining the potential on bit line BL0 at ground potential GND and maintaining the potential on bit line BL1 at write potential VCCW to cause a write current Irw to flow from bit line BL1 to bit line BL0. Then, data is written into storage area L2.
A reading operation for storage area L2 is described below. Referring to FIG. 27, data is read from storage area L2 by maintaining the potential on bit line BL0 at read potential VCCR and maintaining the potential on bit line BL1 at ground potential GND to cause a read current Irr to flow from bit line BL0 to bit line BL1. Then, data is read from storage area L2.
It is also seen from the above that, in storage area L2, the direction in which the current flows in the writing operation is opposite to that of the current flowing in the reading operation. Moreover, respective writing currents in writing data into storage areas L1 and L2 flow in opposite directions respectively. Similarly, respective reading currents in reading data from storage areas L1 and L2 flow in opposite directions respectively.
It is accordingly essential to control the potential on each bit line BL for the writing operation of the NROM.
FIG. 28 illustrates a writing operation for nonvolatile memory cells arranged in the memory cell array as shown in FIG. 22.
Referring to FIG. 28, an operation of writing data of an H (logical high) level into storage area L1 of a nonvolatile memory cell MC1 shown in FIG. 28 is described below.
A word line WL1 is selected, and the potential on bit line BL1 is maintained at write potential VCCW while the potential on bit line BL2 is maintained at ground potential GND. At this time, in nonvolatile memory cell MC1, write current Ifw flows from the node connected to bit line BL1 to the node connected to bit line BL2. Data is accordingly written into storage area L1. Here, in a nonvolatile memory cell MC0 adjacent to nonvolatile memory cell MC1, an unwanted current I1 flows if the potential on bit line BL0 is lower than the potential on bit line BL1. The unwanted current I1 impedes power savings and, in addition, the unwanted current I1 could cause any malfunction of the memory cell array. Control is thus important of the potential on each bit line BL for the writing operation of the NROM.
Moreover, conventional semiconductor memory devices such as the NROM for example can write only one bit at a time into a memory cell, which means that there is a problem of a low throughput.
One object of the present invention is to provide a semiconductor memory device capable of writing data without malfunction. Another object of the present invention is to provide a semiconductor memory device with an improved throughput.
According to one aspect of the present invention, a semiconductor memory device includes a plurality of word lines arranged in the direction of rows, a plurality of bit lines arranged in the direction of columns, a plurality of memory cells, and a write circuit. The memory cells are arranged in the row direction and in the column direction and each have at least one storage area for storing data therein. The write circuit writes multiple data into the memory cells. The memory cells arranged in the row direction are connected in series and have respective gates connected to a word line placed in the row direction. The bit lines are connected correspondingly to the memory cells. The memory cells each store multiple data of at least three bits according to the amount of charge held in the storage area. The write circuit includes a bit line selection circuit and a potential supply circuit. The bit line selection circuit selects a plurality of bit lines connected to memory cells to be written. The potential supply circuit supplies a plurality of predetermined potentials according to a combination of the multiple data to the selected bit lines. Here, the selected bit lines include a bit line connected to the drain of the memory cells to be written and a bit line connected to the source of the memory cells to be written. The potential supply circuit supplies a predetermined first potential to the bit line connected to the drain and supplies a second potential determined according to the combination of the multiple data to the bit line connected to the source.
The semiconductor memory device of the present invention thus supplies the potential according to the combination of multiple write data, to the source of the memory cell to be written. As data of at least three bits can be written into one memory cell, the throughput is improved. Further, as the bit line selection circuit selects a plurality of bit lines and the potential supply circuit supplies different potentials respectively to the bit lines, a predetermined potential can be applied to any bit line connected to a memory cell into which data is to be written. Moreover, bit lines connected to memory cells other than the memory cell to be written enter the floating state. Accordingly, it is possible to prevent current from flowing out into the memory cells not to be written.
According to another aspect of the present invention, a semiconductor memory device includes a semiconductor substrate having a main surface, a memory cell array including a plurality of memory cells, and a write circuit applying a write potential to a selected one of the plurality of memory cells. The memory cells each include first and second conductive regions, a channel region, a first insulating film, a charge storage film, a second insulating film, and a conductive layer. The first and second conductive regions are formed on the main surface of the semiconductor substrate, the channel region is formed at the main surface of the semiconductor substrate and between the first conductive region and the second conductive region, channel hot electrons being generated in the channel region in a writing operation. The first insulating film is formed on the main surface of the semiconductor substrate and on the channel region, the charge storage film is formed on the first insulating film and having a plurality of storage areas, the second insulating film is formed on the charge storage film, and the conductive layer is formed on the second insulating film. The write circuit sets a potential difference between the first conductive region and the second conductive region of the memory cell at a potential difference determined according to a combination of multiple data written into the memory cell in writing operation.
The semiconductor memory device as discussed above is thus capable of writing multiple data according to the potential difference between the first and second conductive regions of the memory cell, which provides an improved throughput.
According to a further aspect of the present invention, a semiconductor memory device includes a semiconductor substrate of a first conductivity type having a main surface, a plurality of first conductive regions of a second conductivity type formed on the main surface of the semiconductor substrate at predetermined intervals therebetween, a plurality of second conductive regions of the first conductivity type formed on the main surface of the semiconductor substrate, the second conductive regions formed respectively in respective regions of the first conductive regions, and a plurality of memory cell arrays formed respectively in respective regions of the second conductive regions. The memory cell arrays each include a plurality of memory cells. The memory cells each include third and fourth conductive regions formed on the main surface of the semiconductor substrate, a channel region formed at the main surface of the semiconductor substrate and between the third conductive region and the fourth conductive region, channel hot electrons being generated in the channel region in a writing operation, a first insulating film formed on the main surface of the semiconductor substrate and on the channel region, a charge storage film formed on the first insulating film and having a plurality of storage areas, a second insulating film formed on the charge storage film, and a conductive layer formed on the second insulating film, A predetermined potential is supplied to the first conductive regions and the second conductive regions.
The semiconductor memory device is configured as discussed above to allow memory cell array blocks to be erased block by block. Accordingly, the potential of the semiconductor substrate can speedily be changed to reduce the erasure time.
Moreover, as there are a plurality of memory cell array blocks, the junction capacitance between the diffusion bit lines and the semiconductor substrate can be reduced relative to the conventional structure.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.